(1) Field of the Invention
The present invention relates to methods used to form semiconductor devices, and more specifically to a method used to form a composite structure comprised of a barrier layer on an underlying metal silicide layer, with the composite structure located at the bottom of a contact hole opening, and formed prior to formation of a metal plug structure in the contact hole opening.
(2) Description of Prior Art
The use of metal silicide layers on specific semiconductor conductive regions, such as gate structures, or source/drain regions, have resulted in decreased word line, and bit line resistance, allowing increased metal oxide semiconductor field effect transistor (MOSFET), device performance to be realized. The formation of metal silicide layers can in most cases be performed using self-alignment procedure, in which a metal layer is blanket deposited, then annealed to form the desired metal silicide layer on regions in which the metal layer resided on underlying conductive regions such as on polysilicon gate structures, and on silicon source/drain regions, located adjacent to the polysilicon gate structure. Unreacted metal, located on non-conductive regions, such as insulator spacers on the sides of the polysilicon gate structure, is then selectively removed resulting in the metal silicide layers, self aligned on underlying conductive regions.
The metal layer, used for metal silicide, is usually obtained via plasma vapor deposition (PVD), procedures, conformally deposited on the non-severe topographies offered by gate structures and adjacent source/drain regions. However in some cases metal silicide layers have to be formed on conductive regions located at the bottom of high aspect ratio contact holes. The narrow diameter, and depth of the high aspect ratio contact hole, present a difficult topography for the PVD metal to contour. The ability to deposit the desired thickness of metal on the conductive region exposed at the bottom of the high aspect ratio contact hole can however be increased via use of a more directional metal deposition procedure. Therefore this invention will describe a method of directionally depositing a metal layer on a conductive region located at the bottom of a high aspect ratio contact hole, excluding deposition on the sides of the high aspect ratio contact hole. Subsequent anneal cycles, performed in specific ambients, result in the formation of the desired metal silicide layer on the underlying conductive region, and result in the selective formation of the desired a barrier layer, located on the newly formed metal silicide layer. Prior art such as Lee et al, in U.S. Pat. No. 5,552,340, describe a method of forming a barrier layer on an underlying metal silicide layer, which is located on a conductive region exposed at the bottom of a contact hole opening. However that prior art, unlike the present invention in which the barrier layer is selectively formed only on metal silicide layers, deposits the barrier layer, resulting in barrier layer located on the sides of the contact hole, thus decreasing the space available in the contact hole for a subsequent conductive plug structure.